The semiconductor industry has advanced considerably in the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the metal-oxide-semiconductor transistor also follows this trend. As the size of the devices is scaled down, the fabrication of these transistors confronts more issues than ever in recent years. For example, high performance CMOS technology has been developed for achieving high packing density wafer for ultra large scale integrated (ULSI) circuits. The cost for the scaled devices is the parasitic effect which will degrade the RC delay and source and drain series resistance.
Hot carrier is another important issue to degrade the performance of the devices although the supply voltage is lowered to 2.5 V for 0.25 micron MOS. In order to provide reliable MOSFETs, many structures of the MOSFET have been proposed. The prior art has reported that an ion implantation with high dose nitrogen for doping into the polysilicon gate and silicon substrate will improve the performance of the deep sub-micron devices. For example, one approach of the prior art to improve the hot carrier resistance is the use of a NICE (nitrogen implantation into CMOS gate electrode and source and drain) structure. The NICE structure is proposed by T. Kuroi, et al., in IEDM Tech. Dig., p325, 1993, entitled "Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source and Drain) Structure for High Reliability and High Performance 0.25 .mu.m Dual Gate CMOS". In this structure, the surface channel PMOS with the p+ poly gate has been investigated in place of the buried channel with n+ poly gate due to the superior short channel behavior. This NICE structure exhibits nitrogen implanted n+ and p+ gates and nitrogen implanted p+ source and drain. The hot carrier problem will be effectively improved by incorporating nitrogen into the gate oxide with nitrogen implantation on the polysilicon gate.
However, the high dose (higher than 4E15 atom/cm.sup.2) nitrogen implantation will cause a drastic increase in sheet resistance of poly-Si gate, therefore the operation speed of devices will be degraded. Please refer to the article "Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors with Lightly Doped Drain Structure", S. Shimizu, et al., Jpn. J. Appel. Phys., vol. 35, p.802, 1996. The hot carrier degration in LDD n-MOS is caused by the generation of interface states or electron traps in the sidewall spacers. For the NICE structure, the nitrided gate oxide under the gate electrode is not effective in suppressing the generation of interface state electron traps. Thus, S. Shimizu proposed a NISW (nitrogen implantation in the silicon oxide sidewall spacers) structure to solve the aforesaid issue. The problem can be suppressed due to the dangling bonds and weakened bonds formed at the interface between the sidewall spacers and the silicon substrate are occupied by the segregated nitrogen atoms.
In order to increase operation speed, the self-aligned metal silicided process has developed for many years. The technology is used to achieve the purpose of reducing the resistance of the gate, the source and drain. The fast operation speed is a basic requirement for ultra-short channel MOSFET. M. T. Takagi, et al. provide a method of forming silicided process in IEDM, Tech. Dig., p.455, 1996. The self-aligned silicided contact technology is the popular method to reduce the resistance of the gate, drain and source electrode. For example, a metal layer, such as Ti, Pt, Co, W, Ni, Cr etc., is sputtered on the substrate, and the gate. Then, a rapid thermal annealing (RTA) at 350 to 700 degrees centigrade is performed to react the metal with the gate and the substrate. Then, a stripping step is used to remove the non-reactive metal on the side wall spacers of the gate. Therefore, the silicide layers are self-aligned formed on gate, source and drain regions.
Further, an article reported that the spacers having oxynitride can suppress the short channel effects or reverse short channel effect. Please refer to the article proposed by P. G. Y. Tsui, et al., in IEDM Tech. Dig., p.501, 1994, entitled "Suppression of MOSFET Reverse Short Channel Effect by N.sub.2 O Gate Poly Reoxidation Process".